1. Field of the Invention
The present invention relates to an electric power consumption reducing technique at a stopping time in an amplifying circuit, particularly, a low noise amplifier used in a high frequency band of a wireless communication system, etc.
2. Description of the Related Art
FIG. 1 is a constructional view of a conventional low noise amplifier (hereinafter called “LNA”) for a high frequency.
This LNA is assembled into a high frequency LSI of one chip manufactured by directly forming an active element such as a transistor and a diode and a passive element such as a resistor, an inductor, a capacitor, etc. on a silicon substrate by a CMOS process technique.
This LNA has a capacitor 2 and an inductor 3 constituting a filter circuit for interrupting a direct electric current from an input signal IN given to a node 1, and fetching a signal of a predetermined frequency area. A cascode-connected amplifying section is connected to the output side of this inductor 3. The amplifying section has an N-channel MOS transistor 4 of a depression type of an initial stage (hereinafter called “DMOS”) and a normal N-channel MOS transistor (hereinafter called “NMOS”) 5 of the next stage. The DMOS 4 has characteristics in which a channel is formed and the DMOS 4 attains a turning-on state by implanting ions into a gate area of the normal NMOS even when a gate bias is 0 V.
The inductor 3 is connected to the gate of the DMOS 4 of the initial stage, and the source of this DMOS 4 is connected to the ground through an inductor 6 for impedance matching. The drain of the DMOS 4 is connected to the source of the NMOS 5 of the next stage. This NMOS 5 is set to a gate grounding type in which the gate of the NMOS 5 is connected to an electric power source voltage VDD. The drain of the NMOS 5 is connected to the electric power source voltage VDD through an inductor 7 for a load, and is also connected to a node 8 for outputting an output signal OUT.
Further, this LNA has a bias generating circuit 9 for generating a negative bias voltage to set the DMOS 4 to a turning-off state and reduce a consumed electric current when an amplifying operation is unnecessary in a standby mode. When a control signal CON is given to the bias generating circuit 9, the bias generating circuit 9 generates a negative voltage approximately able to set the DMOS 4 to the turning-off state. When no control signal CON is given to the bias generating circuit 9, the bias generating circuit 9 outputs a grounding voltage GND. The output side of the bias generating circuit 9 is connected to the gate of the DMOS 4 through a resistor 10.
When the amplifying operation is performed by this LNA, the operation of the bias generating circuit 9 is stopped and the grounding voltage GND is outputted. Thus, the grounding voltage GND is given as a bias voltage in the gate of the DMOS 4 through the resistor 10, and this DMOS 4 attains the turning-on state.
A direct current component and a signal of an unnecessary area are removed from the input signal IN inputted to the node 1 through the capacitor 2 and the inductor 3, and this input signal IN is given to the gate of the DMOS 4. This input signal is then amplified by the cascode amplifier using the DMOS 4 and the NMOS 5, and an output signal OUT is outputted from the node 8.
On the other hand, for example, when a transmitter-receiver is transmitting a signal and no amplifying operation using the LNA is required, the bias generating circuit 9 is operated by the control signal CON and generates a negative voltage. The output voltage of the bias generating circuit 9 is applied to the gate of the DMOS 4 through the resistor 10. Thus, the electric current flowed to the DMOS 4 and the NMOS 5 of the cascode amplifier is stopped and the consumed electric current is reduced.
There are Japanese Patent Kokai No. 7-193441 (patent document 1), Japanese Patent Kokai No. 11-265593 (patent document 2), etc. as the prior art.
The above LNA has the bias generating circuit 9 for generating the negative voltage to set the DMOS 4 to the turning-off state. A circuit utilizing a charge pump is normally used in the bias generating circuit 9. However, problems exist in that the circuit construction is large-sized in the charge pump, and self electric power consumption of the charge pump itself is also increased. For example, in a negative voltage charge pump of the above patent literature 2, four transistor elements and four diode elements are used and three capacitor elements are used.